TUTORIAL
Thermal Modeling of Electronic Components and Packages
 Lorenzo Codecasa Politecnico di Milano, Milan, Italy |
Nowadays we are witnessing an ever-increasing need of thermal characterisation of electronic components and packages. Firstly, in this tutorial it will be shown how electrical networks modeling electronic circuits can be coupled to properly defined thermal networks in order to derive electro-thermal networks able to accurately model thermal effects in electronic circuits by SPICE-like simulation. Precisely, a physical-based definition of junction temperatures of electronic components will be introduced. It will be shown that this definition of junction temperature leads to thermal networks that preserve the thermodynamic properties of heat conduction equations in electronic devices and can be represented by passive RC multi-ports. A Model Order Reduction (MOR) approach tailored for these thermal networks, implemented in the code FAst Novel Thermal Analysis Simulation Tool for Integrated Circuits (FANTASTIC) and now available in commercial software, will be shown to allow a very efficient extraction of Compact Thermal Models (CTMs), and to approximate with any a priori error bound the port responses of the thermal networks. The application of this tool to state-of-the-art electronic case studies will also be presented in detail. Secondly, in this tutorial it will be shown how such results on CTMs have been extended for the extraction of Boundary Condition Independent (BCI) CTMs for Computational Fluid Dynamics electronic cooling simulation. Precisely, the notion of junction temperature will be shown to allow also the modeling of the boundary of electronic components or packages, in such a way to allow to model the coupling of the electronic component or package to all surrounding environments. This approach allows to overcome previous approach based on DELPHI-liked CTMs. Its implementation in the FANTASTIC BCI code, now also available in commercial software, will be shown by applications to state-of-the-art electronic case studies. Several derivations of previous results will also be presented. In particular, it will be shown how to exploit in practical applications the structure function defining the RC transmission line model equivalent to a one-port thermal network, coming from the definition of junction temperature. Also, it will be shown how the presented approach to extract CTMs has been extended to extract parametric models, very useful for calibration, and to extract nonlinear models, crucial for power electronic circuits. |
| Lorenzo Codecasa received the Ph.D. degree in electronics engineering from Politecnico di Milano, Milan, Italy, in 2001. Since 2002, he has been working as an Assistant, then as an Associate, and lastly as a Full Professor of electrical engineering with the DEIB Department of the same University. In his research areas, he has authored or coauthored more than 250 articles in refereed international journals and conference proceedings. His main research contributions are in the theoretical analysis and the computational investigation of electronic circuits and electromagnetic fields. In Stanford University’s ranking, he is listed as one of the world’s 2% most influential scientists. He is particularly active in the research of heat transfer and thermal management of electronic components and packages, in which he has been introducing original approaches to the extraction of compact thermal models. Some of these techniques are becoming available in market-leading commercial software. Dr. Codecasa received the Harvey Rosten Award for Excellence (twice) in 2015 and 2022 and three best papers awards at THERMINIC in 2014, 2017, and 2019. He is currently an Associate Editor for IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY. He has served as a Program Chair, the Vice-General Chair, and the General Chair of THERMINIC. | |
KEYNOTE
Multiphysics and Multidomain Modeling of
Semiconductor IC Packaging and Systems
 Rajen Murugan Texas Instruments, Inc., Dallas (TX), USA |
Transistor/chip scaling has reached the point of diminishing returns and is becoming more complex and expensive at each node. Advanced packaging technologies show promise by bridging the gap in the “More than Moore” Era. However, advanced packaging technologies challenge traditional package design verification tools and methodologies. Complex miniaturization and integration exacerbate coupled multiphysics (e.g., electrical, thermal, mechanical) and multidomain (chip-package-PCB system) interactions. As such, without a paradigm shift in the traditional design verification modeling approach, potential business impacts are highly likely (viz costly re-spins, increased design cycle time, and time-to-market). Coupled multiphysics and system co-design (MSC-D) is emerging as the renewed modeling methodology to ensure first-pass design success. This presentation reviews the development and implementation of an MSC-D methodology for designing high-performance, cost-effective IC complex packaging solutions. The methodology is validated against silicon laboratory measurements on two IC current sensor types – a precision shunt resistor sensor and a high-precision, high-voltage (600V) Hall-Effect current sensor. State-of-the-art progress, challenges, and opportunities in multiphysics system co-design are also discussed. |
| Dr. Rajen Murugan specializes in developing multiphysics system co-design simulation and modeling methodologies for advanced IC packaging and systems. He is currently a Distinguished Member of the Technical Staff (DMTS) with Texas Instruments, Inc. He has 31 granted (US and Canada) patents and 62 under review at the USPTO. He has published over 50 papers in peer-reviewed IEEE journals and conferences. Dr. Murugan holds a Ph.D. in Applied Electromagnetics from the University of Manitoba, Canada. He is an Affiliate Assistant Professor with the University of Washington EE Department, a Distinguished Lecturer for the IEEE Electronics Packaging Society (EPS), an Associate Editor for the IEEE Transactions on CPMT journal, a Senior Member of IEEE, the founder of the IEEE EPS Dallas Chapter, and the Chair of the IEEE Dallas Section (Region 5). | |
KEYNOTE
MagIC – Making Magnetics Disappear onto Silicon
Enabling Power Supply on Chip (PwrSoC)
and Power Supply in Package (PwrSiP)
 Cian Ó Mathúna Tyndall National Institute, University College Cork, Ireland |
The trend in power delivery for processors and other complex SOC platforms is moving away from Point of Load (POL) power to integrated voltage regulation (IVR). This is facilitating the concept of granular power whereby large arrays of dc-dc converters are integrated within the processor package thereby enabling dramatic reduction in overall system energy. This paradigm shift has been enabled by the dramatic miniaturisation of magnetic inductors using thin-film magnetic cores on silicon and PCB-embedded structures to replace bulky wire-wound devices. This talk will discuss the commercial emergence of magnetics-on-silicon technology (MagIC) and associated PCB-embedded magnetics technologies which are enabling Power Supply on Chip and Power Supply in Package platforms. This emerging space of vertical power delivery is transforming the industry ecosystem for processor and SOC power management. It is also being enabled by the recent focus on Heterogeneous Integration and Chiplet platforms for 2.5D and 3D packaging as evidenced in the EU Chips Act and the USA Chips Act. The technologies will be introduced along with the performance capabilities and improvements over conventional magnetics and Point of Load power. The discussion will also consider Heterogeneous Integration of these components with processors using 2.5D and packaging and the emerging Micro Transfer Printing. |
| Cian Ó Mathúna is Head of MicroNano Systems at Ireland’s Tyndall National Institute. His research, over three decades, into the miniaturisation and integration of magnetics onto silicon, has played a key role in disruptive developments in integrated power management for processors in portable electronics and high performance computing. Using semiconductor processing of thin-film magnetics, Ó Mathúna’s team have made bulky power magnetic components disappear onto silicon chips. Referred to as MagIC, Tyndall’s magnetics-on-silicon technology has been licensed to two of the world’s leading consumer electronics companies as well as a leading semiconductor foundry. In 2008, Ó Mathúna founded the International Workshop on Power Supply on Chip (PwrSoC) which has become a highly-influential flagship workshop for IEEE Power Electronics Society and US-based Power Sources Manufacturers Association (PSMA). Through his leadership, and his extensive collaborations with world-leading industry players in Europe, USA and Asia, Ó Mathúna has had a significant influence on the emergence of a global supply-chain for PwrSoC that, in 2021, has seen high-volume production of magnetics-on-silicon in commercial product. Prof. Ó Mathúna is an IEEE Fellow and, in 2021, received the IEEE Power Electronics Society Technical Achievement Award for Integration and Miniaturisation of Switching Power Converters and also received an EARTO (European Association of Research and Technology Organisations) Impact Innovation Award. | |
KEYNOTE
Solving the Challenges of High-Speed/High-Bandwidth
Interconnects for Future System-in-Packages
 Kemal Aygün Intel Corporation, Chandler (AZ), USA |
With the emergence of new applications such as artificial intelligence, future electronic systems need to provide increasingly improved performance. One area where the performance demand has been scaling very aggressively is for interconnecting different components by means of system-in-packages with high-speed/high-bandwidth signaling. To address this demand, future system-in-package architectures and designs require innovations in package technologies, high-speed signaling analysis and validation methods and tools, and standardization. This presentation will review some of the recent developments in electronic packaging from scaling of traditional technologies to new advanced packaging technologies for both on- and off-package interconnects. It will also summarize some of the key challenges and solutions for the corresponding electrical methodologies and metrologies that can be used for design, analysis, and validation of such packages. Finally, some recent advances on standardization of on-package high-speed signaling interconnects will be presented with some thoughts on future scaling. |
| Kemal Aygün received the Ph.D. degree in electrical and computer engineering from the University of Illinois at Urbana-Champaign, Urbana, IL, USA, in 2002. In 2003, he joined the Intel Corporation, Chandler, AZ, USA, where he is currently an Intel Fellow and manages the High Speed I/O (HSIO) team in the Electrical Core Competency group. He has co-authored five book chapters, more than 90 journal and conference publications, and holds 91 U.S. patents. His research interests include novel technologies along with electrical modeling and characterization techniques for microelectronic packaging. Dr. Aygün was the General Chair of the 2020 IEEE Electrical Performance of Electronic Packaging and Systems Conference. He is an IEEE Fellow and has been acting as a Distinguished Lecturer for the IEEE Electronics Packaging Society (EPS); a co-chair of the EPS Technical Committee on Electrical Design, Modeling and Simulation; and an associate editor for the IEEE Transactions on Components, Packaging and Manufacturing Technology. | |